Specification :

With the fast expansion of business scopes, Lepos is gradually aware of the importance of design capability of one company, therefore, Lepos employs electronic engineers with rich experience in the field of PCB design. Lepos wishes to provide more considerate services to every honored customer by perfecting its business and services scopes. Customer intents to realize the design of a PCB with specific functions only needs to tell Lepos his/ her requirements and the relevant data of the PCB. After confirming the accuracy of all information, Lepos can accomplish the task in a very short lead time. The tools used by Lepos for PCB layout include PADS, Mentor Expedition, and Cadence Allegro.
The PCB design capabilities of Lepos are as follows:
Maximum designed layers: 22 layers
Maximum PIN count: 48963
Minimum via: 8 MIL ( 4 Mil laser hole)
Minimum line width: 2.4 MIL
Minimum line spacing: 4 MIL
Maximum BGA count in a single PCB: 44
Minimum BGA PIN pitch: 0.4 mm
Highest speed signal: 10G CML differential signals
Shortest lead time: 6 days for SI, placement, routing for 20000 pin PCB